To perform data transfer between a memory LSI (large scale integrated circuit) and an MPU (microprocessor) at a high speed (high frequency), impedances of transfer systems must be matched to reduce reflection-induced distortion of transfer waveforms. Some high-speed synchronous SRAM (static random access memory) products achieve impedance matching by adjusting impedance of an output driver to a resistance value of a resistance element connected to a dedicated LSI pin.
Transition time (rising/falling edges) during output of data to be transferred should be preferably delayed up to the limit of transfer frequency to suppress (1) signal reflection within package, and (2) simultaneous switching output noise due to package inductor (waveform disturbance due to ringing). Accordingly, output transition time (slew rate) must be controlled so that a data window width during data transfer is maximized. In high-speed synchronous SRAM products, slew rate control has been performed by load control or the like on an LSI mounting board, not by an output driver. The investors have found the existence of the following official gazettes relating to the above-mentioned output impedance control and slew rate control by investigation into prior arts after the present invention.
[Patent publication 1] JP-A No. 242835/1998
[Patent publication 2] JP-A No. 156618/2001
[Patent publication 3] JP-A No. 135102/2002
In patent publication 1, a transistor for output impedance control is disposed independently of a transistor for slew rate control. Rise time is controlled by applying shot pulses to the gate of the transistor for slew rate control, and an output voltage level is determined by the transistor for impedance control. In this way, slew rate and impedance can be controlled independently.
In patent publication 2, an output circuit is provided with open drain buffers that increase sequentially in transistor size, and a slew rate control system has an n-bit counter comprising PLL, frequency divider, EOR, pulse generator, and delayer. A counter is incremented or decremented every half cycle of a clock generated by PLL, and transistors (small-size transistors) having higher impedance are successively turned on earlier, or transistors having lower impedance are successively turned off earlier, whereby a level rises (falls) n/2 cycle later. An open drain buffer for impedance control is newly added to finally control impedance. A slew rate control device for thus stabilizing slew rate is disclosed.
In patent publication 3, an impedance matching circuit comprises a third transistor of first conduction type disposed between a serial connection point between a first transistor and a second transistor, and an external terminal, and a fourth transistor of second conduction type connected in parallel with it. Impedance matching with transmission lines is achieved by parallel combined impedance between the third transistor of the first conduction type and the fourth transistor of the second conduction type. Gate widths of individual transistors forming the impedance matching circuit are reduced to reduce the occupation area of an output circuit having a slew rate control function and an impedance matching function within a chip.
With the technique disclosed in the patent publication 1, since different transistors are used for impedance control and slew rate control, the number of transistors connected to LSI pins increases and pin capacity increases. There is a problem in that this parasitic capacitance increases reflection noise in signal transfer. With the technique disclosed in patent publication 2, a final impedance value is determined in the state in which the size of buffer to perform slew rate control is fixed, and the size of buffer to perform impedance control is variable. Therefore, there is a problem in that, when manufacturing process and operating environment change, a driving force of slew rate control buffer changes, and rise/fall time changes depending on conditions. With the technique disclosed in patent publication 3, since a transistor for slew rate control is connected in series with a transistor for impedance matching, slew rate and impedance cannot be set independently. Also, when manufacturing process and operating environment change, slew rate changes.